FIG. 1 diagrammatically illustrates the overall system configuration of a conventional multiport crosspoint switch architecture of the type that may be used for video signal transmission networks and the like. As shown therein, a plurality N (e.g., eight in the illustrated example) of video inputs (derived from video sources not shown) are coupled via a plurality of input ports 10-1, . . . , 10-8 to a set (e.g., eight) of input buffers 11. Input buffers 11 and an associated set (e.g., eight) of output buffers 17 are necessary, because the crosspoint switch to which respective pluralities of input and output ports are to be connected exhibit parasitic resistance and capacitance, which degrades the signal quality—hence the need for input/output buffering.
The N input buffers 11 have their respective outputs coupled to N input ports of an N×N (8×8 in the example) crosspoint switch matrix 13. Switch matrix 13 has a corresponding plurality of N outputs coupled to output drivers 15, that are coupled via (N=eight) output buffers 17, to an associated set (e.g., eight) of output ports 21-1, . . . , 21-8. Each output port 21 is coupled by way of a prescribed impedance (e.g., a 75 ohm resistor 23), which matches the impedance of a driven line (e.g., a 75 ohm cable 25), which serves as a video output port 26 and is terminated by a (75 ohm) resistor 27 coupled to ground. Control of the interconnections through the switch matrix 13 is effected through a set of control lines of a multilink control cable 31, in accordance with signals (such as those supplied by input and output select lines, command lines, etc.) supplied by a supervisory switch control processor (not shown).
A fundamental shortcoming of the conventional multiport crosspoint switch architecture of FIG. 1 is the fact that it is unidirectional—providing signal transport only from input ports 10 to output ports 21. This implies that if the switch architecture is to be used for bidirectional signalling, the various ports must be designated in advance as to which pins are to be used for inputs and which pins are to be used for outputs. Moreover, when used for symmetrical bidirectional signalling, only half the input/output pins are available for each direction.
In addition to the conventional unidirectional crosspoint switch architecture of the type shown in FIG. 1, the prior art includes bidirectional transceiver arrangements, to which opposite ends of a bidirectional signal transport cable may be terminated, as diagrammatically illustrated in FIG. 2. In accordance with this arrangement, a relatively ‘west’ end 41 of a bidirectional signal transport cable 40 is terminated by a first dual port transceiver 50, while a relatively ‘east’ end 42 of the bidirectional signal transport cable 40 is terminated by a second dual port transceiver 60. By dual port transceiver is meant that the transceiver has both an input port and an output port, in addition to its connection with the bidirectional signal transport cable 40.
More particularly, considering the architecture and operation of the ‘west’ end dual port transceiver 50, for example, the transceiver is comprised of a first transconductance amplifier 70 and a second transconductance amplifier 80. An input port 101 is coupled to a non-inverting (+) input terminal 71 of the first amplifier 70 and to the inverting (−) input terminal 82 of the second amplifier 80. The inverting (−) input terminal 72 of the first amplifier 70 is coupled to a reference potential terminal 74 (e.g., ground), while the non-inverting (+) input terminal 81 of the second amplifier 80 is coupled in common with the output node 73 of the first amplifier 70, and terminates the ‘west’ end 41 of the cable 40. A termination resistor 43 is coupled to ground from the output node 73. The output node 83 of the second amplifier 80 serves as the output port 101 for the ‘west’ end dual port transceiver 50. The architecture of the ‘east’ end dual port transceiver 60 is configured in the same manner as the ‘west’ end dual port transceiver 50 and will not be described here. As shown, the ‘east’ end dual port transceiver 60 has an input port 111 and an output port 112.
In operation, when a signal is applied to the input port 102 of the ‘west’ end dual port transceiver 50, it is coupled to the non-inverting (+) input terminal 71 of the first amplifier 70 and to the inverting (−) input terminal 82 of the second amplifier 80. This signal appears at the output node 73 of the first amplifier for transport over the cable plant 40 to the ‘east’ end dual port transceiver to be delivered to output port 112 thereof. From the output node 73 of the first amplifier, the input signal is also applied to the non-inverting (+) input 81 of amplifier 80. Since the input signal is applied in antiphase to the two inputs 81 and 82 of amplifier 80, the input signal is effectively canceled by amplifier 80, so that it does not appear at output port 102. On the other hand, a signal received from the ‘east’ end dual port transceiver 60 will be coupled via the ‘west’ end 41 of the cable 40 to the non-inverting (+) input 81 of amplifier 80, so that it appears at its output node 83 and thereby the output port 102 of ‘west’ end dual port transceiver 50.
Now although the transceiver architecture of FIG. 2 provides an interface for bidirectional signaling, it is hardware intensive—requiring two transconductance amplifiers per transceiver—and requires a substantial signal drive, since driving the signal line also entails driving a termination impedance (e.g., 50 ohm resistor) to ground. It should also be noted that the transceiver architecture of FIG. 2 has been associated with the interfacing of signals with a bidirectional cable—not a crosspoint switch.